https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112707
--- Comment #15 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by HaoChen Gui <guih...@gcc.gnu.org>: https://gcc.gnu.org/g:46e342b985e6b4058db73875103cced2666e84e2 commit r14-6391-g46e342b985e6b4058db73875103cced2666e84e2 Author: Haochen Gui <guih...@gcc.gnu.org> Date: Mon Dec 11 08:40:34 2023 +0800 rs6000: Enable lrint<mode>si2 on old archs with stfiwx enabled The powerpc 32-bit processors (e.g. 5470) supports "fctiw" instruction, but the instruction can't be generated on such platforms as the insn is guard by TARGET_POPCNTD. The root cause is SImode in float register is supported from Power7. Actually implementation of "fctiw" only needs stfiwx which is supported by the old 32-bit processors. This patch enables "fctiw" expand for these processors. gcc/ PR target/112707 * config/rs6000/rs6000.md (expand lrint<mode>si2): New. (insn lrint<mode>si2): Rename to... (*lrint<mode>si): ...this. (lrint<mode>si_di): New. gcc/testsuite/ PR target/112707 * gcc.target/powerpc/pr112707-1.c: New.
