[Bug target/113469] RISC-V: Illegal Insn for test case 920501-8.c when make linux for rv32

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113469

--- Comment #1 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <pa...@gcc.gnu.org>:

https://gcc.gnu.org/g:d40b3c1e439db05c835b6bd4fd5bba58fda71dd6

commit r14-8442-gd40b3c1e439db05c835b6bd4fd5bba58fda71dd6
Author: Juzhe-Zhong <juzhe.zh...@rivai.ai>
Date:   Fri Jan 26 14:46:21 2024 +0800

    RISC-V: Fix incorrect LCM delete bug [VSETVL PASS]

    This patch fixes the recent noticed bug in RV32 glibc.

    We incorrectly deleted a vsetvl:

            ...
            and     a4,a4,a3
            vmv.v.i v1,0                 ---> Missed vsetvl cause illegal
instruction report.
            vse8.v  v1,0(a5)

    The root cause the laterin in LCM is incorrect.

          BB 358:
            avloc: n_bits = 2, set = {}
            kill: n_bits = 2, set = {}
            antloc: n_bits = 2, set = {}
            transp: n_bits = 2, set = {}
            avin: n_bits = 2, set = {}
            avout: n_bits = 2, set = {}
            del: n_bits = 2, set = {}

    cause LCM let BB 360 delete the vsetvl:

          BB 360:
            avloc: n_bits = 2, set = {}
            kill: n_bits = 2, set = {}
            antloc: n_bits = 2, set = {}
            transp: n_bits = 2, set = {0 1 }
            avin: n_bits = 2, set = {}
            avout: n_bits = 2, set = {}
            del: n_bits = 2, set = {1}

    Also, remove unknown vsetvl info into local computation since it is
unnecessary.

    Tested on both RV32/RV64 no regression.

            PR target/113469

    gcc/ChangeLog:

            * config/riscv/riscv-vsetvl.cc
(pre_vsetvl::compute_lcm_local_properties): Fix bug.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/pr113469.c: New test.