[Bug target/113872] New: PERM<{0},a,{3,4,5,6}> is not producing SHL (for little-endian) and USHR for big-endian

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113872

            Bug ID: 113872
           Summary: PERM<{0},a,{3,4,5,6}> is not producing SHL (for
                    little-endian) and USHR for big-endian
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Keywords: missed-optimization
          Severity: enhancement
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: pinskia at gcc dot gnu.org
  Target Milestone: ---
            Target: aarch64

Take:
```
#define vect64 __attribute__((vector_size(8)))

void f(vect64  unsigned short *a)
{
  *a = __builtin_shufflevector((vect64 unsigned short){0},*a, 3,4,5,6);
}
```

This should produce:
```
        ldr     d31, [x0]
        shl d31, d31, 16
        str     d31, [x0]
```
For little-endian

I suspect this is just a missing `vec_shl_M` pattern.