https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817
--- Comment #15 from Vineet Gupta <vineetg at gcc dot gnu.org> ---
(In reply to Vineet Gupta from comment #14)
> 2. implement gcc toggle -mrvv-vector-bits=zvl which essentially copies the
> xxx from -march string
Done:
commit 0a01d1232ff0a8b094270fbf45c9fd0ea46df19f
Author: Pan Li <pan2...@intel.com>
Date: Fri Feb 23 15:37:28 2024 +0800
RISC-V: Introduce gcc option mrvv-vector-bits for RVV
This patch would like to introduce one new gcc option for RVV. To
appoint the bits size of one RVV vector register. Valid arguments to
'-mrvv-vector-bits=' are:
* scalable
* zvl
The scalable will pick up the zvl*b in the march as the minimal vlen.
For example, the minimal vlen will be 512 when march=rv64gcv_zvl512b
and mrvv-vector-bits=scalable.
The zvl will pick up the zvl*b in the march as exactly vlen.
For example, the vlen will be 1024 exactly when march=rv64gcv_zvl1024b
and mrvv-vector-bits=zvl.
The internal option --param=riscv-autovec-preference will be replaced
by option -mrvv-vector-bits. Aka:
* -mrvv-vector-bits=scalable indicates
--param=riscv-autovec-preference=scalable
* -mrvv-vector-bits=zvl indicates
--param=riscv-autovec-preference=fixed-vlmax
You can also take -fno-tree-vectorize for
--param=riscv-autovec-preference=none.
The internal option --param=riscv-autovec-preference is unavailable after
this
patch.
