https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114288
--- Comment #13 from dave.anglin at bell dot net --- On 2024-03-10 12:15 a.m., law at gcc dot gnu.org wrote: > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114288 > > --- Comment #12 from Jeffrey A. Law <law at gcc dot gnu.org> --- > Aren't we compiling for PA2.0? If so, shouldn't we have a full 14 bit offset > support, even when a load/store hits the FP register file (feel free to > correct > me if I'm wrong, it's only been 20 years since I worked on this stuff ;-) Unfortunately, the PA2.0 relocation for 14-bit offsets in floating-point loads and stores is broken and can't be used on linux. Works fine on hpux. Needs to be fixed. > > So I don't really see why the offsets are an issue here. At this time, we are limited to 5-bit offsets for floating-point loads and stores. > > > If we were compiling for PA1.0/PA1.1, then yes, there's a real issue, but it's > with allowing the larger offsets as a legitimate address. That's lying to the > compiler, reload in particular and as I said, it's ultimately going to > backfire > -- even with the workaround since you're going to have DImode loads/stores to > the FP register file due to xmpyu or potentially even memcpy and friends. I > already tried what you're doing years ago. It's doomed to failure. > > You might think this is a reload problem. But I'm far from convinced. It > smells much more like a PA backend issue to me. I think the problem is with pa_secondary_reload. There is code in pa_emit_move_sequence to handle reloads for for floating-point loads/stores from REG+D addresses but it isn't being used. In non-pic code, the reloads appear to be handled correctly. In pic code, reload doesn't know how to handle a REG+D address where the REG contains the address of a symbol_ref: (insn 10 11 12 2 (set (reg/f:SI 146) (mem/u/c:SI (lo_sum:SI (reg:SI 113) (unspec:SI [ (symbol_ref:SI ("indirect_child") <var_decl 0xf78e81b8 indirect_child>) ] UNSPEC_DLTIND14R)) [0 S4 A32])) "beta.c":18:32 42 {*pa.md:2195} (expr_list:REG_DEAD (reg:SI 113) (expr_list:REG_EQUIV (symbol_ref:SI ("indirect_child") <var_decl 0xf78e81b8 indirect_child>) (nil)))) In theory, it seems to me reload could try reloading D to a register. The offsets are limited to 14 bits and the ldo instruction can handle that directly.
