https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114490
--- Comment #4 from Kang-Che Sung <Explorer09 at gmail dot com> --- 1. I just read "AMD64 Architecture Programmer's Manual - Volume 3: General-Purpose and System Instructions" (https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24594.pdf) It has a clearer wording in the "SAL / SHL" section: "If the shift count is 0, no flags are modified." Just mention for reference. 2. I still don't believe there is no chance of optimizing this thing, but it requires GCC to track the state of the FLAGS register. I don't know if GCC can do this internally. If GCC can't do this for now, that's OK for me (the example I posted can be rewritten to another pattern that might produce even smaller code in x86). But maybe label this as a WONTFIX and not INVALID?
