[Bug target/114506] New: RISC-V: expect M8 but M4 generated with dynamic LMUL

[deminhan at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114506

            Bug ID: 114506
           Summary: RISC-V: expect M8 but M4 generated with dynamic LMUL
           Product: gcc
           Version: unknown
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: deminhan at gcc dot gnu.org
  Target Milestone: ---

we expect M8 when using following code and options, but M4 generated.

-march=rv64gcv_zba_zbb_zvl256b -mabi=lp64d -mrvv-max-lmul=dynamic -O3 

float a[32000],b[32000],c[32000],d[32000];
float aa[256][256],bb[256][256],cc[256][256];

void s2275()
{
        for (int i = 0; i < 256; i++) {
            for (int j = 0; j < 256; j++) {
                aa[j][i] = aa[j][i] + bb[j][i] * cc[j][i];
            }
           a[i] = b[i] + c[i] * d[i];
        }
}

generated asm:
.L2:
        vsetvli a4,s0,e32,m4,ta,ma
        slli    t4,a4,2
        li      a5,0
.L3:
        add     a3,a7,a5
        add     a1,a0,a5
        add     a2,a6,a5
        vle32.v v4,0(a3)
        vle32.v v8,0(a1)
        vle32.v v12,0(a2)
        add     a3,t1,a5
        addi    a5,a5,1024
        vfmadd.vv       v4,v12,v8
        vse32.v v4,0(a3)
        bne     a5,t3,.L3
        vle32.v v8,0(t6)
        vle32.v v4,0(t0)
        vle32.v v12,0(t2)
        sub     s0,s0,a4
        add     a0,a0,t4
        add     a6,a6,t4
        add     a7,a7,t4
        add     t1,t1,t4
        vfmadd.vv       v4,v12,v8
        add     t6,t6,t4
        add     t0,t0,t4
        add     t2,t2,t4
        vse32.v v4,0(t5)
        add     t5,t5,t4
        bne     s0,zero,.L2