[Bug middle-end/114733] [14] Miscompile with -march=rv64gcv -O3 on riscv

[rguenth at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114733

--- Comment #3 from Richard Biener <rguenth at gcc dot gnu.org> ---
So the issue is that we do

  switch (induction_type)
    {
    case vect_step_op_neg:
      if (TREE_CODE (init_expr) != INTEGER_CST
          && TREE_CODE (init_expr) != REAL_CST)
        {
          /* Check for backend support of NEGATE_EXPR and vec_perm.  */
          if (!directly_supported_p (NEGATE_EXPR, vectype))
            return false;

          /* The encoding has 2 interleaved stepped patterns.  */
          vec_perm_builder sel (nunits, 2, 3);
          machine_mode mode = TYPE_MODE (vectype);
          sel.quick_grow (6);
          for (i = 0; i < 3; i++)
            {
              sel[i * 2] = i;
              sel[i * 2 + 1] = i + nunits;
            }

but this scheme doesn't work for a V1DImode vector type.