https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115091
Alexander Monakov <amonakov at gcc dot gnu.org> changed:
What |Removed |Added
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CC| |amonakov at gcc dot gnu.org
--- Comment #3 from Alexander Monakov <amonakov at gcc dot gnu.org> ---
(In reply to andi from comment #2)
> > That said, I heard CPUs have prefetchers that recognize this kind of list
> > walking. I wonder why they wouldn't then also be able to speculate the
> > load value like you say.
>
> These are on the L2 or L3 level, not L1. This is about hiding L1
> latencies, which normally doesn't have a prefetcher.
Richard is correct in the sense that Apple M1 CPUs do that. Intel is not
holding the IPC crown these days ;)
