[Bug target/115169] [14/15 regression] ICE in loongarch bootstrap with checking: RTL check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115169

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
     Ever confirmed|0                           |1
   Target Milestone|---                         |14.2
             Status|UNCONFIRMED                 |NEW
            Summary|[14 regression] ICE in      |[14/15 regression] ICE in
                   |loongarch bootstrap with    |loongarch bootstrap with
                   |checking: RTL check:        |checking: RTL check:
                   |expected code 'reg', have   |expected code 'reg', have
                   |'const_int' in rhs_regno,   |'const_int' in rhs_regno,
                   |at rtl.h:1934               |at rtl.h:1934
   Last reconfirmed|                            |2024-05-21

--- Comment #5 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Confirmed via visual inspecting the code:
```
(define_expand "mov<mode>cc"
  [(set (match_operand:GPR 0 "register_operand")
        (if_then_else:GPR (match_operator 1 "comparison_operator"
                         [(match_operand:GPR 2 "reg_or_0_operand")
                          (match_operand:GPR 3 "reg_or_0_operand")])))]

```
```
  rtx op0 = XEXP (operands[1], 0);
  rtx op1 = XEXP (operands[1], 1);
...

      if ((REGNO (op0) == REGNO (operands[2])
           || (REGNO (op1) == REGNO (operands[3]) && (op1 != const0_rtx)))
          && (GET_MODE_SIZE (GET_MODE (op0)) < word_mode))
        {


```

There is no check to make sure op0/op1/operands[2]/operands[3] are registers
before calling REGNO on them.

This code was introduced by r14-3511-gc28c579f0dd9cd .