https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117477
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
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Status|WAITING |NEW
--- Comment #5 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to Dhruv Chawla from comment #4)
> (In reply to Andrew Pinski from comment #3)
> > Do you have a testcase which comes from some real code that shows the issue
> > or is this just noticed from the small testcase you produced?
>
> Hi, I noticed this occurring in SPEC2017 while diffing changes before and
> after applying a patch. It does not happen very often though, it just piqued
> my curiosity.
>
> > As I mentioned it is a wash but only due to the pair allocation that aarch64
> > can do. On other targets where the pair allocation does not happen, it is
> > usually a win.
>
> Should it still be preferred to do pair allocation on aarch64 then?
I doubt it. As shown by my testcase in comment #2.
Maybe there is a way to improve this inside the RA, to say if there is an odd #
of callee saved registers used, then using a callee is cheaper than a stack
location. But I am not 100% sure this will be in a hot loop and the saving will
be small I think.
