https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118562
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Ever confirmed|0 |1
CC| |rsandifo at gcc dot gnu.org
Summary|SEGV in late-combine |[15 Regression] SEGV in
|(rtl_ssa::function_info::re |late-combine
|move_use) |(rtl_ssa::function_info::re
| |move_use)
Last reconfirmed| |2025-01-20
Status|UNCONFIRMED |NEW
Target Milestone|--- |15.0
--- Comment #4 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Confirmed.
This is related to frm (floating point rounding mode register):
trying to combine definition of r69 in:
67: frm:SI=frm:SI
into:
63: v1:V2SF={(unspec[const_vector,0x2,0x2,0x2,0x2,0x7,vl:SI,vtype:SI,frm:SI]
91)?v1:V2SF-v2:V2SF:unspec[zero:DI] 90}
REG_EQUIV [s3:DI]
successfully matched this instruction to pred_subv2sf:
(set (reg:V2SF 97 v1 [orig:148 vect__3.12_19 ] [148])
(if_then_else:V2SF (unspec:V2BI [
(const_vector:V2BI [
(const_int 1 [0x1]) repeated x2
])
(const_int 2 [0x2]) repeated x4
(const_int 7 [0x7])
(reg:SI 66 vl)
(reg:SI 67 vtype)
(reg:SI 69 frm)
] UNSPEC_VPREDICATE)
(minus:V2SF (reg:V2SF 97 v1 [orig:149 MEM <vector(2) floatD.36>
[(floatD.36 *)h_29 clique 1 base 1] ] [149])
(reg:V2SF 98 v2 [orig:150 MEM <vector(2) floatD.36> [(floatD.36
*)&bD.2797 clique 1 base 0] ] [150]))
(unspec:V2SF [
(reg:DI 0 zero)
] UNSPEC_VUNDEF)))
63: v1:V2SF={(unspec[const_vector,0x2,0x2,0x2,0x2,0x7,vl:SI,vtype:SI,frm:SI]
91)?v1:V2SF-v2:V2SF:unspec[zero:DI] 90}
REG_EQUIV [s3:DI]
successfully matched this instruction to pred_subv2sf:
(set (reg:V2SF 97 v1 [orig:148 vect__3.12_19 ] [148])
(if_then_else:V2SF (unspec:V2BI [
(const_vector:V2BI [
(const_int 1 [0x1]) repeated x2
])
(const_int 2 [0x2]) repeated x4
(const_int 7 [0x7])
(reg:SI 66 vl)
(reg:SI 67 vtype)
(reg:SI 69 frm)
] UNSPEC_VPREDICATE)
(minus:V2SF (reg:V2SF 97 v1 [orig:149 MEM <vector(2) floatD.36>
[(floatD.36 *)h_29 clique 1 base 1] ] [149])
(reg:V2SF 98 v2 [orig:150 MEM <vector(2) floatD.36> [(floatD.36
*)&bD.2797 clique 1 base 0] ] [150]))
(unspec:V2SF [
(reg:DI 0 zero)
] UNSPEC_VUNDEF)))
original cost = 0 + 4 + 4 (weighted: 31.999999), replacement cost = 4 + 4
(weighted: 31.999999); keeping replacement
verify found no changes in insn with uid = 63.
I am not sure if representing frm as a normal SI register is something which is
ok but I could be wrong.
