[Bug target/120930] New: [16 Regression] RISC-V: Miscompile at -O[23] with zvl256b -mrvv-vector-bits=zvl since r16-1645-g309dbcea2ca

[ewlu at rivosinc dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120930

            Bug ID: 120930
           Summary: [16 Regression] RISC-V: Miscompile at -O[23] with
                    zvl256b -mrvv-vector-bits=zvl since
                    r16-1645-g309dbcea2ca
           Product: gcc
           Version: 16.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: ewlu at rivosinc dot com
  Target Milestone: ---

Testcase:
long long s;
unsigned m[23][23];
signed char n[3][23];
long long a[3][23][23];
unsigned short b[23][23];
int main() {
  for (int p = 0; p < 23; ++p)
    for (int q = 0; q < 3; ++q)
      m[p][q] = 561435;
  for (int p = 0; p < 3; ++p)
    for (int q = 0; q < 23; ++q)
      n[p][q] = 3;

  for (_Bool p = 0; p < 1; p = 109)
    for (signed char q = m[p][p] - 27; q < (char)405393777824 + 119; q++) {
      a[p][q][q] = 0;
      b[q][q] = n[p][q];
    }

  for (int p = 0; p < 3;)
    for (int q; p < 23; ++p)
      for (q = 0; q < 23; ++q)
        s = b[p][q];
  __builtin_printf("%llu\n", s);
}

Commands:
# -O2
> /scratch/ewlu/daily-upstream-build/build-gcv/bin/riscv64-unknown-linux-gnu-gcc
>  -march=rv64gcv_zvl256b -O2 -mrvv-vector-bits=zvl red.c -o user-config.out 
> -fsigned-char -fno-strict-aliasing -fwrapv 
> QEMU_CPU=rv64,vlen=256,rvv_ta_all_1s=true,rvv_ma_all_1s=true,v=true,vext_spec=v1.0,zve32f=true,zve64f=true
>  timeout --verbose -k 0.1 4 
> /scratch/ewlu/daily-upstream-build/build-gcv/bin/qemu-riscv64 user-config.out 
> 1
0
# -O1
> /scratch/ewlu/daily-upstream-build/build-gcv/bin/riscv64-unknown-linux-gnu-gcc
>  -march=rv64gcv_zvl256b -O1 -mrvv-vector-bits=zvl red.c -o user-config.out 
> -fsigned-char -fno-strict-aliasing -fwrapv 
> QEMU_CPU=rv64,vlen=256,rvv_ta_all_1s=true,rvv_ma_all_1s=true,v=true,vext_spec=v1.0,zve32f=true,zve64f=true
>  timeout --verbose -k 0.1 4 
> /scratch/ewlu/daily-upstream-build/build-gcv/bin/qemu-riscv64 user-config.out 
> 1
3

Removing -mrvv-vector-bits=zvl makes the miscompile disappear

Found via fuzzer