https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121878
Bug ID: 121878
Summary: ICE in riscv_sched_variable_issue, at
config/riscv/riscv.cc:10239 with -O2
-mcpu=tt-ascalon-d8
Product: gcc
Version: 16.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: bergner at gcc dot gnu.org
Target Milestone: ---
After Jeff's commit r16-3640-g2b7afb69ab4236 which fixed the ordering of the
RISC-V pipeline models, it exposed a typo in the Ascalon pipeline description
which leads to an ICE:
linux:~$ cat ice.c
typedef int __attribute__((__vector_size__ (32))) vec;
vec
foo (vec x, vec y)
{
return x / y;
}
linux:~$ gcc -S -O2 -mcpu=tt-ascalon-d8 ice.c
during RTL pass: sched1
ice.c: In function 'foo':
ice.c:6:1: internal compiler error: in riscv_sched_variable_issue, at
config/riscv/riscv.cc:10239
6 | }
| ^
0x4f1cd35 internal_error(char const*, ...)
/home/bergner/gcc/gcc-fsf-mainline-ascalon/gcc/diagnostic-global-context.cc:786
0x4f2c80c fancy_abort(char const*, int, char const*)
/home/bergner/gcc/gcc-fsf-mainline-ascalon/gcc/diagnostics/context.cc:1787
0x24e19ee riscv_sched_variable_issue
/home/bergner/gcc/gcc-fsf-mainline-ascalon/gcc/config/riscv/riscv.cc:10239
0x479a925 schedule_block(basic_block_def**, void*)
/home/bergner/gcc/gcc-fsf-mainline-ascalon/gcc/haifa-sched.cc:6928
0x1e63454 schedule_region
/home/bergner/gcc/gcc-fsf-mainline-ascalon/gcc/sched-rgn.cc:3213
0x1e64289 schedule_insns()
/home/bergner/gcc/gcc-fsf-mainline-ascalon/gcc/sched-rgn.cc:3535
0x1e64b59 rest_of_handle_sched
/home/bergner/gcc/gcc-fsf-mainline-ascalon/gcc/sched-rgn.cc:3739
0x1e64cc6 execute
/home/bergner/gcc/gcc-fsf-mainline-ascalon/gcc/sched-rgn.cc:3849
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
The problem is in the vector insn reservations like the following:
(define_insn_reservation "tt_ascalon_d8_vec_idiv_single" 13
(and (eq_attr "tune" "tt_ascalon_d8")
(eq_attr "type" "vidiv")
(eq_attr "mode" "SF"))
"tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
We check the "mode", but we are incorrectly checking for a scalar mode instead
of the V*SI modes, so this insn doesn't get handled correctly leading to the
ICE.
