https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122209
Bug ID: 122209
Summary: reassoc? with bit masking
Product: gcc
Version: 16.0
Status: UNCONFIRMED
Keywords: missed-optimization
Severity: enhancement
Priority: P3
Component: tree-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: rdapp at gcc dot gnu.org
Target Milestone: ---
Target: riscv
The following code
int
foo (int t)
{
t += 3 + 3 * t;
t &= 0xFFF;
t += 3 + 3 * t;
t &= 0xFFF;
t += 3 + 3 * t;
t &= 0xFFF;
t += 3 + 3 * t;
t &= 0xFFF;
t += 3 + 3 * t;
t &= 0xFFF;
t += 3 + 3 * t;
t &= 0xFFF;
t += 3 + 3 * t;
t &= 0xFFF;
t += 3 + 3 * t;
t &= 0xFFF;
t += 3 + 3 * t;
t &= 0xFFF;
return t;
}
should be optimized to "return 4095" but isn't on riscv.
For x86 this works via a series of combine optimizations.
The gist is that the individual insns/patterns are complex
enough to see through just enough insns that everything
reduces to "large number" & 0xFFF.
On riscv the individual instruction patterns are not powerful
enough to see ahead far enough so we end up with a lot of
additions, shifts and ands.
I'm not sure reassoc is the right place to tackle this as it
doesn't handle sequences with mixed operators (+, *, &) well.
The only exception being sums of multiplications IIRC.
But reassoc or not, shouldn't we have a generic way to optimize
that short of target-specific instruction combinations?
