https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122486
Bug ID: 122486
Summary: RISC-V: The intrinsic for the vsetvli instruction
generates assembly that does not match the intrinsic's
documented semantics
Product: gcc
Version: 16.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: sundongya at nucleisys dot com
Target Milestone: ---
#include <stdlib.h>
#include <riscv_vector.h>
int main() {
size_t avl = 4;
volatile size_t vl = __riscv_vsetvl_e32m4(avl);
return 0;
}
Under -O0, the same source line "volatile size_t vl=__riscv_vsetvl_e32m4(avl);"
compiles to "vsetvli a5,a5,e8,m1,ta,ma" when built with GCC (both 32-bit and
64-bit modes).
The resulting vtype is therefore "e8,m1", not the expected "e32,m4", so the
instruction does not match the intrinsic’s documented semantics.
With Clang -O0, the identical code yields the correct "vsetvli
a1,a1,e32,m4,ta,ma" in both 32-bit and 64-bit variants; only Clang emits the
right instruction.
rv32gcc: https://godbolt.org/z/94TEPEzhh
rv64gcc: https://godbolt.org/z/ssxW43eKE
rv32clang: https://godbolt.org/z/9YP5Mc9jv
rv64clang: https://godbolt.org/z/e9bKesvcn
