https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122534
--- Comment #6 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Uros Bizjak <[email protected]>: https://gcc.gnu.org/g:584f50a6e405f057ab41fb5416aea5820f15c9cd commit r16-5016-g584f50a6e405f057ab41fb5416aea5820f15c9cd Author: Uros Bizjak <[email protected]> Date: Mon Nov 3 20:22:10 2025 +0100 i386: Allow memory op in operand 1 predicate of *test<mode>_1 insn patterns [PR122534] Combine tries to combine AND RTX with memory operand: Trying 12 -> 13: 12: {r106:DI=r99:DI&[r100:DI*0x8+r103:DI];clobber flags:CC;} REG_UNUSED flags:CC 13: flags:CCZ=cmp(r106:DI,0) REG_DEAD r106:DI but fails to match instruction: (set (reg:CCZ 17 flags) (compare:CCZ (and:DI (reg:DI 99 [ shifttmp_6 ]) (mem:DI (plus:DI (mult:DI (reg/v:DI 100 [ i ]) (const_int 8 [0x8])) (reg/v/f:DI 103 [ p ])) [1 MEM[(long unsigned int *)p_8(D) + i_14 * 8]+0 S8 A64])) (const_int 0 [0]))) because corresponding *test<mode>_1 pattern doesn't allow memory operand 1. Allow memory operand 1 by matching operand predicates of *test<mode>_1 family of insns with corresponding *and<mode>_2 insn patterns. The testcase improves from: movl %esi, %ecx movl $1, %eax salq %cl, %rax movq %rax, %rcx xorl %eax, %eax .L4: movq %rcx, %rdx andq (%rdi,%rax,8), %rdx jne .L1 ... to: movl $1, %edx movl %esi, %ecx xorl %eax, %eax salq %cl, %rdx .L4: testq %rdx, (%rdi,%rax,8) jne .L1 ... Also improve pentium pairing in *testqi_1_maybe_si insn pattern. PR target/122534 gcc/ChangeLog: * config/i386/i386.md (@test<mode>_ccno_1): Use <general_szext_operand> as operand 1 predicate. (testqi_ccz_1): Use general_operand as operand 1 predicate. (*testdi_1): Use x86_64_szext_general_operand as operand 1 predicate. (*testqi_1_maybe_si): Use general_operand as operand 1 predicate. Add (n,*a) alternative to allow UV pairing for pentium processor. (*test<mode>_1): Use <general_operand> as operand 1 predicate. gcc/testsuite/ChangeLog: * gcc.target/i386/pr122534.c: New test.
