https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122552
Bug ID: 122552
Summary: RISC-V: Cannot combine vector shift like vsll.vv to
vsll.vx
Product: gcc
Version: 16.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: pan2.li at intel dot com
Target Milestone: ---
During the .vv combine to .vx optimization, we found some of the integer rvv
insn cannot perform that pattern due to lack of necessary rtls. Idealy, we
have a rvv insn like vsll.vv, and vec_dup, then we can combine these into
vsll.vx.
Unfortunately, we do get the pattern after tree.optimized. Give we have sample
code as below:
```
3 │ #define NT uint64_t
4 │
5 │ void
6 │ vsll_vx_0(NT * restrict vd, NT * restrict vs2, NT rs1, unsigned n)
7 │ {
8 │ for (unsigned i = 0; i < n; i++)
9 │ vd[i] = vs2[i] << rs1;
10 │ }
```
When build with " -march=rv64gcv -mabi=lp64d -O3 ~/gcc/__test__/vsll.vx.c -c -S
--param=gpr2vr-cost=0 -o - -fdump-tree-optimized-details"
```
40 │ unsigned int _5;
...
59 │ # vectp_vs2.5_25 = PHI <vectp_vs2.5_24(4), vs2_12(D)(3)>
60 │ # vectp_vd.9_9 = PHI <vectp_vd.9_8(4), vd_14(D)(3)>
61 │ # ivtmp_31 = PHI <ivtmp_32(4), _30(3)>
62 │ _33 = .SELECT_VL (ivtmp_31, POLY_INT_CST [2, 2]);
63 │ ivtmp_26 = _33 * 8;
64 │ vect__4.7_22 = .MASK_LEN_LOAD (vectp_vs2.5_25, 64B, { -1, ... },
_23(D), _33, 0);
65 │ vect__7.8_18 = vect__4.7_22 << _5;
66 │ .MASK_LEN_STORE (vectp_vd.9_9, 64B, { -1, ... }, _33, 0,
vect__7.8_18);
```
It looks we need some changes from the middle-end to perform the combine.
