https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118026
--- Comment #4 from Jeffrey A. Law <law at gcc dot gnu.org> --- We discussed this in the RISC-V meeting today. Mostly to make sure everyone was clear on the earlyclobber question. The RISC-V ISA has widening vector options. So you might have narrow inputs and a wider output. In those scenarios the RISC-V ISA does not generally allow overlap between the input values and output values when the output object has a larger EMUL than the input object. Thus we use the earlyclobber constraint to prevent the register allocator from tying an input to the output when the EMUL of the output operand is larger than the EMUL of the input operand(s). -- There are some limited kinds of overlap allowed; we actually tried to support those for gcc-14 using some new IRA/LRA capabilities at the time. THe RISC-V specific bits for that got reverted over a painful weekend and while we think we can correctly describe the overlap restrictions and allow them in limited circumstances, that code isn't really ready for re-integration at this time. -- So hopefully that indicates where we are and why we have the (necessary) earlyclobbers.
