On Thu, Nov 13, 2025 at 9:58 PM Averill, Charles Charles via Gcc-bugs <[email protected]> wrote: > > Upon re-implementing "vTaskSwitchContext" from FreeRTOS in RISC-V > (implementation attached), the "clz a5, a5" instruction is incorrectly > assembled as 0x60079793, when the RISC-V Zbb extension specification > (https://five-embeddev.com/riscv-bitmanip/1.0.0/bitmanip.html#insns-clz) > specifies that it should be 0x600a9a93.
This list is for automated emails of GCC bugzilla. But in your case this is a bug in GNU binutils which is a different project from GCC (though shared developers and resources in many cases). Either you report it to the binutils list [email protected] or their bugzilla: https://sourceware.org/bugzilla. > > Version: > > GNU assembler (xPack GNU RISC-V Embedded GCC x86_64) 2.43.1 > Copyright (C) 2024 Free Software Foundation, Inc. > This program is free software; you may redistribute it under the terms of > the GNU General Public License version 3 or later. > This program has absolutely no warranty. > This assembler was configured for a target of `riscv-none-elf'. > > I didn't compile these tools, I downloaded them here: > https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack Also since you getting the tools from a github, you might want to report the issue you have directly with them if not already. Thanks, Andrew > > I've also attached the two makefiles used to compile this project.
