[Bug target/122769] RISC-V: Short branch can be elided for alu op

[vineetg at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122769

--- Comment #6 from Vineet Gupta <vineetg at gcc dot gnu.org> ---
And with a different attempt:

+      emit_insn (gen_slt_3 (LT, Xmode, Xmode, *op0, *op0, *op1));

I see a slightly diffeent error.

error: unrecognizable insn:

(insn 8 7 9 2 (set (reg:SI 140)
        (lt:DI (reg:SI 140)
            (const_int 0 [0])))
     (nil))
during RTL pass: vregs

I have a feeling we need to fix the the mode iterators in these patterns.