[Bug tree-optimization/122635] RISC-V: -mrvv-vector-bits=zvl introducing unoptimal vsetivli zero,0 and insns depending on AVL nops

[gkm at rivosinc dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122635

--- Comment #19 from Greg McGary <gkm at rivosinc dot com> ---
Robin's patch fixes both his longer test case, and my reduced one. Gracias! :D