https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122769
--- Comment #10 from Jeffrey A. Law <law at gcc dot gnu.org> ---
So this may be a simple matter of exending the current code.
Right now it uses noce_emit_czero which ultimately is going to require the test
to be EQ/NE. But instead I think we can use something like this to be far more
general:
/* First emit a conditional zero for one operand (such as the shift count).
AND requires a bit of special handling, but is worth the effort as it
happens regularly. */
target = gen_reg_rtx (mode);
target = noce_emit_cmove (if_info, target, GET_CODE (if_info->cond),
XEXP (if_info->cond, 0), XEXP (if_info->cond, 1),
op != AND ? arg1 : const0_rtx, op != AND ?
const0_rtx : arg0);
The advantage is that routine is it uss emit_conditional_move which under the
hood will run through the RISC-V expansion code which handles emitting an sCC
style insn if presented with something other than a simple equality test
against zero. Naturally that other routine (ok_for_condzero_arith or whatever
it is) would need adjustment as well.
That's what we're using in that patch I attached to this BZ. Let me play
around a bit with that.
