[Bug rtl-optimization/123223] New: [16 Regression][gcn] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1946

[burnus at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123223

            Bug ID: 123223
           Summary: [16 Regression][gcn] ICE: RTL check: expected code
                    'reg', have 'subreg' in rhs_regno, at rtl.h:1946
           Product: gcc
           Version: 16.0
            Status: UNCONFIRMED
          Keywords: build, ice-on-valid-code
          Severity: normal
          Priority: P3
         Component: rtl-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: burnus at gcc dot gnu.org
                CC: ams at gcc dot gnu.org
  Target Milestone: ---
            Target: gcn

Building 'libgcc' with gcn (amdgcn-amdhsa) fails (GCC r16-6279-g18c306b1f42e3e)
with:

repos/gcc/libgcc/libgcc2.c: In function ‘__multi3’:
gcc/libgcc/libgcc2.c:538:1: internal compiler error: RTL check: expected code
'reg', have 'subreg' in rhs_regno, at rtl.h:1946
  538 | }
      | ^
0x21b810d internal_error(char const*, ...)
        repos/gcc/gcc/diagnostic-global-context.cc:787
0x8ac9f3 rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int,
char const*)
        repos/gcc/gcc/rtl.cc:770
0x863afe rhs_regno(rtx_def const*)
        repos/gcc/gcc/rtl.h:1946
0x865fa6 rhs_regno(rtx_def const*)
        repos/gcc/gcc/lra-constraints.cc:4314
0x865fa6 curr_insn_transform
        repos/gcc/gcc/lra-constraints.cc:4864
0x104158f lra_constraints(bool)
        repos/gcc/gcc/lra-constraints.cc:5659
0x10279d4 lra(_IO_FILE*, int)
        repos/gcc/gcc/lra.cc:2455
0xfd3a6f do_reload
        repos/gcc/gcc/ira.cc:6070
0xfd3a6f execute
        repos/gcc/gcc/ira.cc:6258

* * *

(gdb) p debug_rtx(x)
(subreg:DI (reg/v:TI 688 [ w ]) 8)


* * *

Reduced testcase:

typedef int DItype __attribute__((mode(DI)));
struct DWstruct {
  DItype low, high
};
typedef union {
  struct DWstruct s;
  __int128 ll
} DWunion;
__int128 __multi3() {
  DWunion vv, w = {};
  w.s.high += vv.s.high + vv.s.low;
  return w.ll;
}