https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123268
Bug ID: 123268
Summary: [16 Regression] Recent change triggers ICE on riscv32
Product: gcc
Version: 16.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: law at gcc dot gnu.org
Target Milestone: ---
This change:
commit f5ddd4ba0ba1b00838e36966fbaf771c581b99ef
Author: Robin Dapp <[email protected]>
Date: Thu Nov 6 13:16:40 2025 +0100
RISC-V: Add VLS modes to autovec iterators.
In order to allow more VLS vectorization, add more VLS modes to the
autovec expanders, as well as some missing VLS modes that I encountered
while
testing.
gcc/ChangeLog:
* config/riscv/autovec.md: Ditto.
* config/riscv/autovec-opt.md: Add VLS modes.
* config/riscv/vector-crypto.md: Ditto.
* config/riscv/vector-iterators.md: Ditto.
* config/riscv/vector.md (@pred_ffs<VB:mode><P:mode>): Ditto.
(@pred_ffs<VB_VLS:mode><P:mode>): Ditto.
Is triggering an ICE on riscv32:
unix//-march=rv32gcv: gcc: gcc.dg/torture/pr77478.c -O2 (test for excess
errors)
unix//-march=rv32gcv: gcc: gcc.dg/torture/pr77478.c -O2 (test for excess
errors)
[ ... ]
It should be visible with a cross compiler using -O2 -march=rv32gcv
-ffast-math.
