[Bug middle-end/123573] [16 Regression] Many aarch64 tests ICEing with invalid gimple since r16-6709-ga4716ece529dfd

[rguenth at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123573

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Last reconfirmed|                            |2026-01-13
           Assignee|unassigned at gcc dot gnu.org      |rguenth at gcc dot 
gnu.org
             Status|UNCONFIRMED                 |ASSIGNED
     Ever confirmed|0                           |1
                 CC|                            |avieira at gcc dot gnu.org,
                   |                            |tnfchris at gcc dot gnu.org

--- Comment #2 from Richard Biener <rguenth at gcc dot gnu.org> ---
 Applying pattern match.pd:11533, gimple-match-4.cc:26294

   vector(4) int _1;
   svint32_t _3;
...
-  _3 = VEC_PERM_EXPR <_1, _1, { 0, 1, 2, 3, ... }>;
+  _3 = _1;

looks like a latent issue in the pattern.  This is the

    (if (known_eq (nelts, nelts_in) && sel.series_p (0, 1, 0, 1))
     { op0; }
     (if (sel.series_p (0, 1, nelts_in, 1))
      { op1; }

case.  previously this was

    (if (sel.series_p (0, 1, 0, 1))
     { op0; }
     (if (sel.series_p (0, 1, nelts_in, 1))
      { op1; }

so I'd say adding another known_eq might work - but with -msve-vector-bits=128
the code still ICEs but might honor known_eq.  Indeed, with

    (if (known_eq (nelts, nelts_in) && sel.series_p (0, 1, 0, 1))
     { op0; }
     (if (known_eq (nelts, nelts_in) && sel.series_p (0, 1, nelts_in, 1))
      { op1; }

the ICE is gone. Unless you add -msve-vector-bits=128.  Using
types_match () instead helps - or do we want V_C_E in the case with
-msve-vector-bits=128?

-  _3 = VEC_PERM_EXPR <_1, _1, { 0, 1, 2, 3 }>;
+  _3 = VIEW_CONVERT_EXPR<svint32_t>(_1);

I'm testing the V_C_E variant.