https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123725

            Bug ID: 123725
           Summary: [16 Regression] highway-1.3.0 -O3 build failure on
                    aarch64: error: this operation requires the SVE ISA
                    extension
           Product: gcc
           Version: 16.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: slyfox at gcc dot gnu.org
  Target Milestone: ---

Initially observed on `highway-1.3.0` as a build failure on -O3 but not lower.
Hopefully not too incorrect reproducer against r16-6902-g1c06e68228226a:

// $ cat bug.cc
struct I {
  int operator*();
  void operator++();
};
bool operator==(I, I);
struct V {
  I begin();
  I end();
};
struct S {
  S(char *);
};
__attribute__((noreturn)) void Abort();
void Trans_NS_detail_TypeName(int, int, char *);
char s[1];
int i;
static S TypeName(int N) {
  Trans_NS_detail_TypeName(i, N, s);
  return s;
}
#pragma GCC aarch64 "arm_sve.h"
#pragma GCC target "+sve"
template <typename, int> using ScalableTag = int;
template <class Test> struct ForeachCountAndMisalign {
  template <typename T, class D> static void h(T, D d) {
    int rng, m;
    V counts;
    for (int count : counts)
      Test::g(d, count, m, rng);
  }
};
struct TestFind {
  template <class D> static void g(D, int, int, int) {
    int __trans_tmp_3 = svcntw_pat(SV_ALL);
    TypeName(__trans_tmp_3);
    Abort();
  }
};
template <int kPow2 = 1> struct ForExtendableVectors {
  template <typename T> static void f(T) {
    ScalableTag<T, kPow2> d;
    ForeachCountAndMisalign<TestFind>::h(float(), d);
  }
};
void ForFloat3264Types() {
  ForExtendableVectors<>::f(float());
  ForExtendableVectors<>::f(float());
}

Triggering:

$ gcc/xgcc -Bgcc -O1 -c bug.cc -o bug.o
# ok
$ gcc/xgcc -Bgcc -O2 -c bug.cc -o bug.o
# ok
$ gcc/xgcc -Bgcc -O3 -c bug.cc -o bug.o
# bad
bug.cc: In function ‘S TypeName(int)’:
bug.cc:18:27: error: this operation requires the SVE ISA extension
   18 |   Trans_NS_detail_TypeName(i, N, s);
      |   ~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~
bug.cc:18:27: note: you can enable SVE using the command-line option ‘-march’,
or by using the ‘target’ attribute or pragma

I think this example should compile.

$ gcc/xgcc -Bgcc -v
Reading specs from gcc/specs
COLLECT_GCC=gcc/xgcc
COLLECT_LTO_WRAPPER=gcc/lto-wrapper
Target: aarch64-unknown-linux-gnu
Configured with: /root/gcc/configure --prefix=/usr --disable-multilib
--disable-bootstrap --disable-lto --disable-libsanitizer
--enable-languages=c,c++ CFLAGS='-O1 -g0' CXXFLAGS='-O1 -g0' LDFLAGS='-O1 -g0'
--target=aarch64-unknown-linux-gnu
Thread model: posix
Supported LTO compression algorithms: zlib zstd
gcc version 16.0.1 20260119 (experimental) (GCC)

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