[Bug target/123381] ICE: maximum number of generated reload insns per insn achieved (90) with -mrvv-vector-bits=zvl

[law at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123381

--- Comment #1 from Jeffrey A. Law <law at gcc dot gnu.org> ---
So carrying over a comment that mistakenly placed elsewhere.  This is the
problematic insn:

(insn 25 15 27 2 (set (reg:RVVM1DI 141 [ vect__4.9 ])
        (if_then_else:RVVM1DI (unspec:RVVMF64BI [
                    (const_vector:RVVMF64BI [
                            (const_int 1 [0x1]) repeated x2
                        ])
                    (const_int 2 [0x2]) repeated x3
                    (const_int 0 [0])
                    (reg:SI 66 vl)
                    (reg:SI 67 vtype)
                ] UNSPEC_VPREDICATE)
            (sign_extend:RVVM1DI (subreg:RVVMF4HI (reg:DI 168) 0))
            (unspec:RVVM1DI [
                    (reg:DI 0 zero)
                ] UNSPEC_VUNDEF))) "j.c":6:8 10885 {pred_extendrvvm1di_vf4}
     (nil))

We need to reload the argument to the sign_extend which generates this:

(insn 39 38 25 2 (parallel [
            (set (reg:RVVMF4HI 169)
                (subreg:RVVMF4HI (reg:DI 168) 0))
            (clobber (reg:DI 170))
        ]) "j.c":6:8 2973 {*movrvvmf4hidi_lra}
     (expr_list:REG_UNUSED (reg:DI 170)
        (nil)))

That in turn generates another reload:

(insn 40 38 39 2 (parallel [
            (set (reg:RVVMF4HI 171)
                (subreg:RVVMF4HI (reg:DI 168) 0))
            (clobber (reg:DI 172))
        ]) "j.c":6:8 2973 {*movrvvmf4hidi_lra}
     (expr_list:REG_UNUSED (reg:DI 172)
        (nil)))

And we'll proceed to looping generating that insns with that same structure
over and over.