https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123760
Bug ID: 123760
Summary: Worse code for FoF loads since r16-6975.
Product: gcc
Version: 16.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: rdapp at gcc dot gnu.org
Target Milestone: ---
Target: riscv
The fix for r16-6975-gca5a68ac280135 included removing the early gimple split
of an FoF load into a load and a read_vl. This early split allowed us to
optimize away the store as well as the csrr vl read.
The fix now makes the VL dependency explicit in RTL, avoiding the segfault, but
with only the RTL passes left we have a hard time getting rid of the store,
some vsetvls, as well as the csrr VL read.
#include "riscv_vector.h"
void foo (int * a)
{
size_t vl;
vint32m1_t v = __riscv_vle32ff_v_i32m1 (a, &vl, 64);
vint32m1_t v2 = __riscv_vadd_vv_i32m1 (v, v, vl);
__riscv_vse32_v_i32m1 (a, v2, 64);
}
-march=rv64gcv -O3
There shouldn't be any store or csrr here. Another instance of the problem is
ffload-3.c in the rvv.exp=vsetvl/* testsuite.
