https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123108
--- Comment #5 from Robin Dapp <rdapp at gcc dot gnu.org> ---
I tried restricting the equiv replacement only to insns with constraints but
that also doesn't help because we then get a MEM as VL operand.
In ira we have:
r180: preferred NO_REGS, alternative NO_REGS, allocno NO_REGS
a20 (r180,l0) best NO_REGS, allocno NO_REGS
a20(r180,l0) costs: GR_REGS:1000000,1000000 MEM:1005000,1005000
causing the spill.
It gets more interesting. Before ira we have:
(insn 72 71 11 2 (set (reg:V32BI 155 [ _2 ])
(if_then_else:V32BI (unspec:V32BI [
(const_vector:V32BI [
(const_int 1 [0x1]) repeated x32
])
(reg:DI 180)
(const_int 2 [0x2]) repeated x2
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(ltu:V32BI (reg:V32HI 156)
(vec_duplicate:V32HI (subreg:HI (reg:DI 178 [ BS_ARG_0 ]) 0)))
(unspec:V32BI [
(reg:DI 0 zero)
] UNSPEC_VUNDEF))) "pr123108.c":7:14 14735
{*pred_cmpv32hi_scalar_narrow}
(expr_list:REG_DEAD (reg:DI 180)
(expr_list:REG_DEAD (reg:V32HI 156)
(nil))))
This is a real insn with constraints. However in ira we canonicalize(?) to:
(insn 72 71 11 2 (set (reg:V32BI 155 [ _2 ])
(if_then_else:V32BI (unspec:V32BI [
(const_vector:V32BI [
(const_int 1 [0x1]) repeated x32
])
(reg:DI 180)
(const_int 2 [0x2]) repeated x2
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(gtu:V32BI (vec_duplicate:V32HI (subreg:HI (reg:DI 137 [
BS_ARG_0.0_4 ]) 0))
(reg:V32HI 156))
(unspec:V32BI [
(reg:DI 0 zero)
] UNSPEC_VUNDEF))) "pr123108.c":7:14 38283
{*pred_cmp_swappedv32hi_scalar}
(expr_list:REG_DEAD (reg:DI 180)
(expr_list:REG_DEAD (reg:V32HI 156)
(nil))))
swapping the comparison. And this insn does _not_ have constraints.
I guess the NO_REG preference then comes from ira seeing that (reg 180) only
has
a single use in (insn 72) but without any constraint?
>From there it all goes downward :)
What I don't know yet is where exactly the swapping happens. One solution
would be to force splitting the insn afterwards.
