[Bug target/123784] [14/15/16 Regression] during RTL pass: early_ra ICE: in operator[], at vec.h:2475 with -O2 -fno-tree-dse -fno-tree-dce -mbig-endian -g

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123784

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to Andrew Pinski from comment #1)
> (gdb) p debug_rtx(ref.base.reg)
> (subreg:OI (reg:V16QI 110 [ _16 ]) 0)


Note the above is awkward paradoxal subreg especially for big-endian. 


CSE2 introduces it.

We start from:
```
(debug_insn 32 15 17 2 (var_location:OI D#1 (reg:OI 118)) -1
     (nil))
(debug_insn 17 32 18 2 (var_location:OI q (debug_expr:OI D#1)) "t.c":9:5 -1
     (nil))
```

To:
```
(debug_insn 33 14 32 2 (var_location:OI D#2 (subreg:OI (reg:V16QI 110 [ _16 ])
0)) -1
     (nil))
(debug_insn 32 33 17 2 (var_location:OI D#1 (debug_expr:OI D#2)) -1
     (nil))
(debug_insn 17 32 18 2 (var_location:OI q (debug_expr:OI D#1)) "t.c":9:5 -1
     (nil))

```

So the subreg is kinda of incorrect as now only describing the upper half of
the register but there is not much to be done as r118 no longer exists. 

Anyways I have a fix.