[Bug target/122051] ICE: in validate_change_or_fail, at config/riscv/riscv-v.cc:6011 with -mrvv-vector-bits=zvl -mcpu=xt-c920

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122051

--- Comment #7 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-15 branch has been updated by Alexandre Oliva
<aol...@gcc.gnu.org>:

https://gcc.gnu.org/g:f30695c5b57f36ea5b7dd98b02719badd9d8984d

commit r15-10785-gf30695c5b57f36ea5b7dd98b02719badd9d8984d
Author: Alexandre Oliva <ol...@adacore.com>
Date:   Wed Feb 4 23:06:40 2026 -0300

    testsuite: riscv: drop -mcpu=xt-c920 tests from gcc-15

    Testcases were backport to gcc-15 that require support for a cpu that
    is not supported by gcc-15.  Drop them.


    for  gcc/testsuite/ChangeLog

            PR target/122051
            PR target/120642
            * gcc.target/riscv/pr122051.c: Remove.
            * gcc.target/riscv/rvv/xtheadvector/pr120642.c: Remove.