https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123994
--- Comment #6 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
At the begining of the function we have:
```
(insn 116 2 3 2 (set (reg:DI 163 [ BS_ARG_3D.2478 ])
(reg:DI 11 a1 [ BS_ARG_3D.2478 ])) "/app/example.c":20:1 -1
(expr_list:REG_DEAD (reg:DI 11 a1 [ BS_ARG_3D.2478 ])
(nil)))
(insn 3 116 4 2 (set (reg/v:DI 150 [ BS_ARG_3D.2478 ])
(reg:DI 163 [ BS_ARG_3D.2478 ])) "/app/example.c":20:1 275
{*movdi_64bit}
(expr_list:REG_DEAD (reg:DI 163 [ BS_ARG_3D.2478 ])
(nil)))
```
There is a loop afterwards where r150 is not changed but is used
And then outside of the loop we have:
BS_ARG_3 < 80 ? BS_ARG_3 : 0
Which is done as:
```
(insn 111 110 112 13 (set (reg:DI 160)
(leu:DI (reg/v:DI 150 [ BS_ARG_3D.2478 ])
(const_int 79 [0x4f]))) "/app/example.c":35:53 discrim 3 438
{*sleu_didi}
(nil))
(insn 112 111 113 13 (set (reg:DI 164)
(neg:DI (reg:DI 160))) "/app/example.c":35:53 discrim 3 17 {negdi2}
(expr_list:REG_DEAD (reg:DI 160)
(nil)))
(insn 113 112 71 13 (set (reg/v:DI 150 [ BS_ARG_3D.2478 ])
(and:DI (reg/v:DI 150 [ BS_ARG_3D.2478 ])
(reg:DI 164))) "/app/example.c":35:53 discrim 3 104 {*anddi3}
(expr_list:REG_DEAD (reg:DI 164)
(nil)))
```
Which was done because of coalescing when going out of ssa (ifcvt.cc created
the above RTL, this was done without zicond enabled but it does not matter in
the end).
accepting this change as far as I know should be ok really because 150 is not
set until after the last use.
late_combine as far as I understand tries not to move instructions around
before reload:
// Moving instructions before register allocation could increase
// register pressure. Only try moving them after RA.
if (reload_completed && can_move_insn_p (use_insn))
use_change->move_range = { use_insn->bb ()->head_insn (),
use_insn->ebb ()->last_bb ()->end_insn () };
So move_range is set to insn as first and last.
So with the loop later_insn seems to do the wrong thing. or something like
that.
insn 111 should be after insn 40 (which is/was inside the loop).
