https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121787
--- Comment #11 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The releases/gcc-15 branch has been updated by Robin Dapp <[email protected]>: https://gcc.gnu.org/g:66bab5582291400713a742dcfcb3deee6542666f commit r15-10811-g66bab5582291400713a742dcfcb3deee6542666f Author: Jeff Law <[email protected]> Date: Mon Jan 19 15:53:22 2026 -0700 [RISC-V][PR rtl-optimization/121787] Work around bad cfglayout interaction with asm goto This is a suggestion from Richi in the PR. The RISC-V backend calls the loop initialization routines during setup for vsetvl insertion/optimization. Right now that uses LOOPS_NORMAL which allows various adjustments to the loop structure. The interaction between those CFG adjustments and asm goto support is putting the CFG into an undesirable state. There's potentially an issue in the CFG layout bits, but we can punt that out by using AVOID_CFG_MODIFICATIONS when calling loop_optimizer_init. My review of the vsetvl code doesn't show any direct need for clean preheaders, latches, etc -- the biggest thing it needs is for infinite loops to be connected to the exit block which is handled outside of loop_optimizer_init. So this is a workaround, but enough to get the PR off the regression list. Waiting for pre-commit CI to do its thing, though it has already passed riscv{32,64}-elf for me. Bootstrap on the Pioneer is in flight. PR rtl-optimization/121787 gcc/ * config/riscv/riscv-vsetvl.cc (pre_vsetvl): Adjust call to loop_optimizer_init to avoid making CFG changes. gcc/testsuite/ * gcc.target/riscv/pr121787-1.c: New test. * gcc.target/riscv/pr121787-2.c: New test. (cherry picked from commit 63e0c271e984a7f63208f3517c110ccb6b33d8e1)
