https://gcc.gnu.org/bugzilla/show_bug.cgi?id=124063
Bug ID: 124063
Summary: Inquiry about code generation differences between GCC
7 and 14 for ARM Cortex-A9 with soft-float ABI
Product: gcc
Version: 14.3.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
Assignee: unassigned at gcc dot gnu.org
Reporter: jiangxuezhi2 at huawei dot com
Target Milestone: ---
I would like to humbly ask for your guidance regarding a code generation
difference I observed between GCC 7 and GCC 14 when targeting ARM Cortex-A9
with soft-float ABI. I’m not sure if this is an expected optimization or
potentially something that could be improved.
eg.
uint32_t test(const void *pAddr, double *plfValue)
{
if ((NULL == pAddr) || (NULL == plfValue)) {
return (0 | 7);
}
*plfValue = (double)(*(const double *)pAddr);
return (0 | 0);
}
Compilation Flags.
-mtune=cortex-a9 -mfpu=vfpv3-d16 -mfloat-abi=softfp -O2
GCC 14 Output:
test:
cmp r1, #0
cmpne r0, #0
vldrne.64 d7, [r0] # Requires 8-byte alignment
movne r3, #0
movne r0, r3
moveq r3, #1
moveq r0, #7
vstrne.64 d7, [r1] # Requires 8-byte alignment
bx lr
GCC 7 Output:
test:
clz r3, r1
cmp r0, #0
lsr r3, r3, #5
moveq r3, #1
cmp r3, #0
bne .L3
push {r4, r5}
ldmia r0, {r4-r5}
mov r0, r3
stm r1, {r4-r5}
pop {r4, r5}
bx lr
.L3:
mov r0, #7
bx lr
Questions:
1. Alignment Safety Concern:
GCC 14 generates VFP instructions (vldrne.64/vstrne.64) that require 8-byte
alignment, but user-space code cannot always guarantee this for generic
pointers. Could you suggest best practices for helping user code detect or
handle such alignment requirements? Are there warnings or static analysis tools
that could help identify this risk?
2. Optimization Change:
Could you help me understand what optimization in GCC 14 leads to this
different code generation? Is this an intentional improvement that assumes
stronger alignment guarantees, or might there be room to make the optimization
more alignment-safe for soft-float ABIs?
