[Bug target/124077] New: [ARM thumb-1 armv8-m.base] Redundant CMP instruction after CC setting instruction

[saaadhu at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=124077

            Bug ID: 124077
           Summary: [ARM thumb-1 armv8-m.base] Redundant CMP instruction
                    after CC setting instruction
           Product: gcc
           Version: 16.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: saaadhu at gcc dot gnu.org
  Target Milestone: ---

For code like below, the ANDS insn already sets the condition code, yet the
compiler generates a redundant CMP.

$ cat repro.c
extern int y;
extern void bar(void);
extern volatile int *p;
#define FILL p[0] = 1; p[1] = 2; p[2] = 3; p[3] = 4; p[4] = 5; p[5] = 6; p[6] =
7;
void foo(int x, int z)
{
  y = x & z;
  if (y)
  {
    FILL FILL FILL FILL FILL;
  }
  else
  {
    bar();
  }
}

$ arm-none-eabi-gcc --version
arm-none-eabi-gcc (GCC) 16.0.1 20260212 (experimental)

$ arm-none-eabi-gcc -march=armv8-m.base -Os repro.c -S -o -
<snip>
        ldr     r3, .L4
        ands    r1, r0
        str     r1, [r3]
        cmp     r1, #0
        beq     .L2

Note that this does not happen for armv6-m - the CMP insn is correctly elided.

$ arm-none-eabi-gcc -march=armv6-m -Os repro.c -S -o -
<snip>
        ldr     r3, .L4
        ands    r1, r0
        str     r1, [r3]
        beq     .L2