[Bug target/123904] Failure to optimize left shift + and sequence on RISC-V

[law at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123904

Jeffrey A. Law <law at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
     Ever confirmed|0                           |1
           Assignee|unassigned at gcc dot gnu.org      |law at gcc dot gnu.org
   Last reconfirmed|                            |2026-03-10
             Status|UNCONFIRMED                 |ASSIGNED

--- Comment #1 from Jeffrey A. Law <law at gcc dot gnu.org> ---
It's actually a shift pair that works well for this case.  Better yet, a shift
pair is independent of rv32/rv64 and doesn't require any extensions.  I've got
a patch for gcc-17.