[Bug target/124956] Improve conditional shift by 6 for leela on risc64

[law at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=124956

--- Comment #1 from Jeffrey A. Law <law at gcc dot gnu.org> ---
Here's a nice simplified testcase.  Compile with -march=rv64gcbv_zicond
-mbranch-cost=4:

int
foo(int cond, int val)
{
  if (cond)
    val *= 64;
  return val;
}

You'll get this code:

        slliw   a5,a1,6
        czero.eqz       a5,a5,a0
        czero.nez       a0,a1,a0
        add     a0,a0,a5
        ret

But what you want is something like

        li      a5,6
        czero.eqz       a0,a5,a0
        sllw    a0,a1,a0
        ret

I'll dig out the old bits we've got, but that should give you some ideas to get
started.   I'd start by wandering into ifcvt.cc's noce_try_cond_arith.