https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125395
Bug ID: 125395
Summary: [RISCV] xtheadvector: vf[n/w]cvt instructions with
static rounding modes generate invalid opcodes
Product: gcc
Version: 17.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: johnrobin044 at gmail dot com
Target Milestone: ---
When compiling for the xtheadvector vendor extension, using standard RISC-V
vector float conversion intrinsics with static rounding modes (e.g., _rtz_,
_rod_) results in unrecognized opcode errors from the assembler.
Compiling:
#include <riscv_vector.h>
#include <stdint.h>
void test_intrins(
vfloat64m4_t src_f64m4,
int64_t *out_rtz_x,
int32_t *out_ncvt_rtz_x,
float *out_ncvt_rod,
int64_t *out_wcvt_rtz_x,
size_t vl
) {
vint64m4_t res_vfcvt_rtz_x = __riscv_vfcvt_rtz_x_f_v_i64m4(src_f64m4, vl);
__riscv_vse64_v_i64m4(out_rtz_x, res_vfcvt_rtz_x, vl);
vint32m2_t res_ncvt_rtz_x = __riscv_vfncvt_rtz_x_f_w_i32m2(src_f64m4, vl);
__riscv_vse32_v_i32m2(out_ncvt_rtz_x, res_ncvt_rtz_x, vl);
vfloat32m2_t res_ncvt_rod = __riscv_vfncvt_rod_f_f_w_f32m2(src_f64m4, vl);
__riscv_vse32_v_f32m2(out_ncvt_rod, res_ncvt_rod, vl);
vint64m4_t res_wcvt_rtz_x = __riscv_vfwcvt_rtz_x_f_v_i64m4(res_ncvt_rod,
vl);
__riscv_vse64_v_i64m4(out_wcvt_rtz_x, res_wcvt_rtz_x, vl);
}
With:
-march=rv64gc_xtheadvector -mabi=lp64d -O2
Will yield:
/tmp/cca835VT.s: Assembler messages:
/tmp/cca835VT.s:20: Error: unrecognized opcode `th.vfcvt.rtz.x.f.v v12,v8'
/tmp/cca835VT.s:25: Error: unrecognized opcode `th.vfncvt.x.f.v.f.w v16,v8'
/tmp/cca835VT.s:34: Error: unrecognized opcode `th.vfncvt.f.f.v.f.w v8,v8'
/tmp/cca835VT.s:36: Error: unrecognized opcode `th.vfwcvt.rtz.x.f.v v12,v8'
Compiler returned: 1
