https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125538
--- Comment #5 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Artemiy Volkov <[email protected]>: https://gcc.gnu.org/g:80b78b2504fba037c4edf7172712210b323dcf32 commit r17-1372-g80b78b2504fba037c4edf7172712210b323dcf32 Author: Artemiy Volkov <[email protected]> Date: Thu Jun 4 14:47:17 2026 +0000 aarch64: define duplication into sub-64-bit AdvSIMD vectors [PR125538] This is a second attempt to deal with the ICE reported in PR125538, triggering when we generate a (vec_duplicate:V4QI (reg:QI)) expression for which we currently lack RTL support. More specifically, this occurs when doing a splat of the most common element in aarch64_expand_vector_init_fallback () at aarch64.cc:25876. This is the alternative approach mentioned in the original commit message at [0], whereby we simply define vec_duplicate patterns for 16-bit and 32-bit destinations. Same tests are added as in [0] (a full test reduced in the comments to the PR, as well as some new vector constructor element combinations in vec_init_5.c and vec-init-23.c). Regtested and bootstrapped on aarch64-linux-gnu. [0] https://gcc.gnu.org/pipermail/gcc-patches/2026-June/719181.html PR target/125538 gcc/ChangeLog: * config/aarch64/aarch64-simd.md (*aarch64_simd_dup_subvector<vcons><mode>): New insn pattern. (*aarch64_simd_dup_subvectorv2qiqi): Likewise. * config/aarch64/iterators.md (VSDUP): New mode iterator. (VCONS): New mode attribute. (vcons): Likewise. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sve/vec_init_5.c: Add new 8/16-bit testcases. * gcc.target/aarch64/vec-init-23.c: Likewise. * gcc.target/aarch64/pr125538.c: New test.
