https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125670
--- Comment #10 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The releases/gcc-15 branch has been updated by Jeff Law <[email protected]>: https://gcc.gnu.org/g:8d3e022a1b839d4226afc36d5842b07e4d976f63 commit r15-11309-g8d3e022a1b839d4226afc36d5842b07e4d976f63 Author: Robin Dapp <[email protected]> Date: Tue Jun 16 06:54:48 2026 -0600 [PATCH] RISC-V: Fix splitter [PR125670]. Hi, In the PR we ICE during vsetvl, expecting a register in the VL operand slot which only contains an immediate 4. Non-VLMAX insns with immediate length have a NULL_RTX in that slot. However, during a split, we erroneously use operand[5] instead of operand[6]. operand[5] is the mask policy and happened to be "1". "1" indicates a VLMAX insn in the avl_type operand. This caused the wrong turn in vsetvl. The patch just corrects the operand number. Regtested on rv64gcv_zvl512b. Going to wait for the CI. Regards Robin PR target/125670 gcc/ChangeLog: * config/riscv/autovec-opt.md: Use avl_type operand number. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr125670.c: New test. (cherry picked from commit d815c8e374c85a36b8df244287ea1a2159cbd950)
