[Bug rtl-optimization/123884] Missed bit manipulation on RISC-V

[law at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123884

--- Comment #3 from Jeffrey A. Law <law at gcc dot gnu.org> ---
So I've added an AND version of that pattern and cleaned things up slightly.  I
get this for the two testcases:


        binv    a0,a0,a1
        sext.w  a0,a0
        ret

        bclr    a0,a0,a1
        sext.w  a0,a0
        ret

Both of which look optimal.  Happy with what I'm seeing so far.