https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125970
Bug ID: 125970
Summary: [17 Regression] cmov side effect causes 14%
HINT/double regression on znver5/GNR at -O2
-mtune=generic -march=x86-64-v3
Product: gcc
Version: 17.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: rtl-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: lili.cui at intel dot com
Target Milestone: ---
Created attachment 64840
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=64840&action=edit
small case
HINT is an older benchmark from the Phoronix Test Suite (small testcase:
hint_minimal.i).
With -O2 -mtune=generic -march=x86-64-v3, commit
52cd02606b906160bf47001a00b446c35d46f15f ("x86: Increase generic tune branch
misprediction cost") causes about a 14% regression on both Znver5 and GNR.
This change converts only one additional branch:
inc = (errio < errjo) + 1;
to cmov. That branch is not on the hot path (it accounts for less than 3% of
total cycles).
However, the generated code is reorganized as a side effect (register
allocation, CFG shape, and instruction scheduling). A similar hot bb becomes
much slower, and the regression comes entirely from there.
It looks like one is in the else BB and the other is in the then BB, and this
is likely related to the BPU.
base:
0.11 │18d:│ movslq -0x4(%rsi,%rcx,4),%rax
0.01 │ │ mov %ecx,%r12d
0.02 │ │ mov %rax,%r11
0.01 │ │ lea (%rax,%rax,8),%rax
0.09 │ │ lea (%r8,%rax,8),%rax
2.19 │ │ vmulsd 0x10(%rax),%xmm9,%xmm11
0.71 │ │ vmovsd %xmm11,0x10(%rdx)
0.00 │ │ vmovsd 0x40(%rax),%xmm1
0.26 │ │ vmovsd %xmm11,0x10(%rax)
0.02 │ │ vmovsd %xmm1,0x40(%rdx)
0.05 │ │ vaddsd 0x38(%rax),%xmm11,%xmm4
0.06 │ │ vmovsd %xmm4,0x40(%rax)
0.10 │ │ vmovsd %xmm4,0x38(%rdx)
2.46 │ │ vmovsd 0x30(%rax),%xmm1
0.01 │ │ vmovsd %xmm1,0x30(%rdx)
0.10 │ │ vmovsd 0x28(%rax),%xmm1
0.13 │ │ vmovsd %xmm1,0x28(%rdx)
0.01 │ │ vmovsd (%rbx),%xmm1
0.05 │ │ vaddsd %xmm1,%xmm4,%xmm3
0.12 │ │ vsubsd %xmm4,%xmm1,%xmm1
0.16 │ │ vmulsd 0x0(%rbp),%xmm1,%xmm1
2.81 │ │ vdivsd %xmm3,%xmm1,%xmm2
1.90 │ │ vcvttsd2si %xmm2,%r14d
0.58 │ │ vcvtsi2sd %r14d,%xmm10,%xmm12
1.81 │ │ vmulsd %xmm3,%xmm12,%xmm3
0.40 │ │ vmovsd %xmm12,0x30(%rax)
0.18 │ │ vucomisd %xmm1,%xmm3
2.81 │ │↓ jp 20f
patch:
0.05 │ d4: movslq -0x4(%rsi,%rcx,4),%rax
0.12 │ mov %ecx,%r14d
0.00 │ mov %rax,%r10
0.01 │ lea (%rax,%rax,8),%rax
0.03 │ lea (%r8,%rax,8),%rax
1.79 │ vmulsd 0x10(%rax),%xmm9,%xmm11
0.84 │ vmovsd %xmm11,0x10(%rdx)
0.00 │ vmovsd 0x40(%rax),%xmm1
0.16 │ vmovsd %xmm11,0x10(%rax)
0.06 │ vmovsd %xmm1,0x40(%rdx)
0.01 │ vaddsd 0x38(%rax),%xmm11,%xmm4
0.15 │ vmovsd %xmm4,0x40(%rax)
0.00 │ vmovsd %xmm4,0x38(%rdx)
2.75 │ vmovsd 0x30(%rax),%xmm1
0.04 │ vmovsd %xmm1,0x30(%rdx)
0.00 │ vmovsd 0x28(%rax),%xmm1
0.08 │ vmovsd %xmm1,0x28(%rdx)
0.05 │ vmovsd 0x0(%rbp),%xmm1
0.02 │ vaddsd %xmm1,%xmm4,%xmm3
0.58 │ vsubsd %xmm4,%xmm1,%xmm1
0.02 │ vmulsd (%r12),%xmm1,%xmm1
1.86 │ vdivsd %xmm3,%xmm1,%xmm2
3.42 │ vcvttsd2si %xmm2,%ebx
0.19 │ vcvtsi2sd %ebx,%xmm10,%xmm12
4.16 │ vmulsd %xmm3,%xmm12,%xmm3
5.12 │ vmovsd %xmm12,0x30(%rax)
0.25 │ vucomisd %xmm1,%xmm3
11.43 │ ↓ jp 157
