https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125716
--- Comment #4 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Artemiy Volkov <[email protected]>: https://gcc.gnu.org/g:4c63fdea7468ff398e8bc6fac5c56fc51123a98c commit r17-1839-g4c63fdea7468ff398e8bc6fac5c56fc51123a98c Author: Artemiy Volkov <[email protected]> Date: Tue Jun 23 10:21:55 2026 +0000 aarch64: split r->w moves for partial AdvSIMD vectors [PR125716] This is a fix for PR125716, where under specific circumstances we end up emitting an insn like: (insn 32 26 27 2 (set (reg:V2HI 63 v31 [orig:130 _13 ] [130]) (reg:V2HI 0 x0 [orig:115 _13 ] [115])) "testcase.c":3:17 1392 {*aarch64_simd_movv2hi} (nil)) for which aarch64_simd_mov instruction variant taking sub-64-bit vector operands there is no (w,r) alternative and things blow up later during reload. This is a problem specifically in the case of reg-reg transfers and only when transfer cost between relevant register classes is 2, which, as I've learned thanks to Andrea's writeup at [0] (and as is confirmed by e.g. gcc/lra-constraints.cc:4245), is a magic value that tells LRA/reload to not try different reloads which would have helped here. The testcase added is a blend between those provided in PR125716 and in PR125947. As stable as affected tuning models may be, I've opted to create a dedicated JSON file for this test to guarantee a GP2FP cost of 2. Bootstrapped and regtested on aarch64-linux-gnu with and without -mtune=octeontx81. [0] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125947#c1 PR target/125716 gcc/ChangeLog: * config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>): Add (?w,r) alternative for VSUB64 types. gcc/testsuite/ChangeLog: * gcc.target/aarch64/aarch64-json-tunings/gp2fp-2.json: New JSON tuning file. * gcc.target/aarch64/simd/pr125716.c: New test.
