https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113779

--- Comment #10 from Oleg Endo <olegendo at gcc dot gnu.org> ---
I've been trying to resurrect some previous work for addressing mode selection
optimization (RTL pass).

This is what current GCC17 produces on SH for the example in the original
description:



_f:
        cmp/pl  r6
        bf      .L11
        .align 2
.L9:
        mov.l   @r4,r1
        dt      r6
        mov.l   r1,@r5
        mov.l   @(4,r4),r1
        mov.l   r1,@(4,r5)
        mov.l   @(8,r4),r1
        mov.l   r1,@(8,r5)
        mov.l   @(12,r4),r1
        mov.l   r1,@(12,r5)
        mov.l   @(16,r4),r1
        mov.l   r1,@(16,r5)
        mov.l   @(20,r4),r1
        mov.l   r1,@(20,r5)
        mov.l   @(24,r4),r1
        mov.l   r1,@(24,r5)
        mov.l   @(28,r4),r1
        mov.l   r1,@(28,r5)
        mov.l   @(32,r4),r1
        mov.l   r1,@(32,r5)
        mov.l   @(36,r4),r1
        mov.l   r1,@(36,r5)
        mov.l   @(40,r4),r1
        mov.l   r1,@(40,r5)
        mov.l   @(44,r4),r1
        mov.l   r1,@(44,r5)
        mov.l   @(48,r4),r1
        mov.l   r1,@(48,r5)
        mov.l   @(52,r4),r1
        mov.l   r1,@(52,r5)
        mov.l   @(56,r4),r1
        mov.l   r1,@(56,r5)
        mov.l   @(60,r4),r1
        add     #64,r4
        mov.l   r1,@(60,r5)
        bf/s    .L9
        add     #64,r5
.L11:
        rts     
        nop


With the additional optimization pass we get proper post-inc utilization
On SH4 we usually don't have post-inc stores, only post-inc loads.

_f:
        cmp/pl  r6
        bf      .L11
        .align 2
.L9:
        mov.l   @r4+,r1
        dt      r6
        mov.l   r1,@r5
        mov.l   @r4+,r1
        mov.l   r1,@(4,r5)
        mov.l   @r4+,r1
        mov.l   r1,@(8,r5)
        mov.l   @r4+,r1
        mov.l   r1,@(12,r5)
        mov.l   @r4+,r1
        mov.l   r1,@(16,r5)
        mov.l   @r4+,r1
        mov.l   r1,@(20,r5)
        mov.l   @r4+,r1
        mov.l   r1,@(24,r5)
        mov.l   @r4+,r1
        mov.l   r1,@(28,r5)
        mov.l   @r4+,r1
        mov.l   r1,@(32,r5)
        mov.l   @r4+,r1
        mov.l   r1,@(36,r5)
        mov.l   @r4+,r1
        mov.l   r1,@(40,r5)
        mov.l   @r4+,r1
        mov.l   r1,@(44,r5)
        mov.l   @r4+,r1
        mov.l   r1,@(48,r5)
        mov.l   @r4+,r1
        mov.l   r1,@(52,r5)
        mov.l   @r4+,r1
        mov.l   r1,@(56,r5)
        mov.l   @r4+,r1
        mov.l   r1,@(60,r5)
        bf/s    .L9
        add     #64,r5
.L11:
        rts     
        nop


On SH2A there's also a post-inc store insn, so that produces:

_f:
        cmp/pl  r6
        bf      .L10
        .align 2
.L8:
        mov.l   @r4+,r0
        dt      r6
        mov.l   r0,@r5+
        mov.l   @r4+,r0
        mov.l   r0,@r5+
        mov.l   @r4+,r0
        mov.l   r0,@r5+
        mov.l   @r4+,r0
        mov.l   r0,@r5+
        mov.l   @r4+,r0
        mov.l   r0,@r5+
        mov.l   @r4+,r0
        mov.l   r0,@r5+
        mov.l   @r4+,r0
        mov.l   r0,@r5+
        mov.l   @r4+,r0
        mov.l   r0,@r5+
        mov.l   @r4+,r0
        mov.l   r0,@r5+
        mov.l   @r4+,r0
        mov.l   r0,@r5+
        mov.l   @r4+,r0
        mov.l   r0,@r5+
        mov.l   @r4+,r0
        mov.l   r0,@r5+
        mov.l   @r4+,r0
        mov.l   r0,@r5+
        mov.l   @r4+,r0
        mov.l   r0,@r5+
        mov.l   @r4+,r0
        mov.l   r0,@r5+
        mov.l   @r4+,r0
        bf.s    .L8
        mov.l   r0,@r5+
.L10:
        rts/n



and the case from comment #8 is fixed, too:

_test_8:
        cmp/pl  r6
        bf      .L16
        .align 2
.L14:
        mov.b   @r5+,r1
        dt      r6
        mov.b   r1,@r4
        bf/s    .L14
        add     #1,r4
.L16:
        rts     
        nop


However, this is still very early and very WIP-ish.  But early results look
promising, I think.

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