https://gcc.gnu.org/bugzilla/show_bug.cgi?id=126771
--- Comment #2 from Tamar Christina <tnfchris at gcc dot gnu.org> --- > /* We may directly use cond with narrowed type to avoid multiple cond > exprs with following result packing and perform single cond with > packed mask instead. In case of widening we better make cond first > and then extract results. */ > if (TYPE_MODE (type) == TYPE_MODE (TREE_TYPE (lhs))) > type = TREE_TYPE (lhs); > > ISTR on aarch64 SVE masks are still "unpacked", Sorta, we also support computed masks. Computed masks, are from SVE2p1 and SME2's multi-vector operations. These instead of having a xx bits per lane, use a specific encoding to say how many registers they cover and what the lanes of these registers are See [1] "SME2 Multi-vector predication" We don't support these in the vectorizer yet but is on our roadmap. [1] https://developer.arm.com/community/arm-community-blogs/b/architectures-and-processors-blog/posts/part4-arm-sme2-introduction
