https://gcc.gnu.org/bugzilla/show_bug.cgi?id=126778
Bug ID: 126778
Summary: ICE compiling perlbench in verify_ssa caused by commit
f87736236260bee8512fbf2441494c71952da6ed
Product: gcc
Version: 17.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: tree-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: bergner at gcc dot gnu.org
Target Milestone: ---
The following test case reduced from perlbench ICEs on trunk when compiling for
riscv:
bergner:~/$ cat bug.i
void glob3(char *sc, short *dc)
{
while (dc && (*dc++ = *sc))
;
}
bergner:~/$ gcc -O3 -march=rv64imv -S bug.i
bug.i: In function 'glob3':
bug.i:1:6: error: PHI node with wrong VUSE on edge from BB 6
1 | void glob3(char *sc, short *dc)
| ^~~~~
.MEM_90 = PHI <.MEM_4(6)>
expected .MEM_82
during GIMPLE pass: vect
bug.i:1:6: internal compiler error: verify_ssa failed
0x5724415 internal_error(char const*, ...)
/home/bergner/gcc/gcc-fsf-mainline-base/gcc/diagnostic-global-context.cc:787
0x24350a0 verify_ssa(bool, bool)
/home/bergner/gcc/gcc-fsf-mainline-base/gcc/tree-ssa.cc:1226
0x1e46523 execute_function_todo
/home/bergner/gcc/gcc-fsf-mainline-base/gcc/passes.cc:2107
0x1e450fc do_per_function
/home/bergner/gcc/gcc-fsf-mainline-base/gcc/passes.cc:1699
0x1e466be execute_todo
/home/bergner/gcc/gcc-fsf-mainline-base/gcc/passes.cc:2152
/home/bergner/gcc/build/gcc-fsf-mainline-debug/gcc/cc1 -fpreprocessed bug.i
-quiet -dumpbase bug.i -dumpbase-ext .i -march=rv64imv -mabi=lp64d
-misa-spec=20191213 -mtls-dialect=trad
-march=rv64imfdv_zicsr_zmmul_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b
-O3 -o bug.s
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
Git bisect identifies the following commit as the culprit:
commit f87736236260bee8512fbf2441494c71952da6ed
Author: Tamar Christina <[email protected]>
AuthorDate: Tue Aug 4 15:31:02 2026 +0100
Commit: Tamar Christina <[email protected]>
CommitDate: Tue Aug 4 15:31:45 2026 +0100
vect: convert do-loop edges properly for
LOOP_VINFO_EARLY_BREAKS_VECT_PEELED [PR126301]
