https://gcc.gnu.org/bugzilla/show_bug.cgi?id=126946

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |14.5

--- Comment #1 from Richard Biener <rguenth at gcc dot gnu.org> ---
So why does RTL if-conversion not produce the fcsel?  (and why do we have such
strange BB order)

The COND_EXPR allows the x86 cmov expander to pattern-match its FP MIN/MAX
operations which match IEEE semantics of m < a ? a : m

On trunk I do see fcsel being used on aarch64 just fine for your testcase,
so what "fixed" it there?

.L3:
        ldr     s31, [x1, x2, lsl 2]
        add     x2, x2, 1
        fabs    s31, s31
        fcmpe   s31, s0
        fcsel   s0, s31, s0, gt
        cmp     x0, x2
        bne     .L3
        ret

We expand from

  _4 = MEM[(const float *)x_9(D) + _20 * 4];
  a_10 = ABS_EXPR <_4>;
  _12 = a_10 > m_16;
  _11 = _12 ? a_10 : m_16;

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