https://gcc.gnu.org/bugzilla/show_bug.cgi?id=126959
--- Comment #6 from Richard Biener <rguenth at gcc dot gnu.org> ---
(In reply to H.J. Lu from comment #1)
> This
>
> diff --git a/gcc/config/i386/x86-tune-costs.h
> b/gcc/config/i386/x86-tune-costs.h
> index bc3bb694349..7574cc4f1ad 100644
> --- a/gcc/config/i386/x86-tune-costs.h
> +++ b/gcc/config/i386/x86-tune-costs.h
> @@ -2119,7 +2119,7 @@ struct processor_costs znver4_cost = {
> 8, 8, /* mask->integer and integer->mask moves */
> {6, 6, 6}, /* cost of loading mask register
> in QImode, HImode, SImode. */
> - {8, 8, 8}, /* cost if storing mask register
> + {6, 6, 6}, /* cost if storing mask register
> in QImode, HImode, SImode. */
> 2, /* cost of moving mask register. */
> /* End of register allocator costs. */
>
> fixes the issue. Richard, can you check if it is OK on znver4?
Official AMD docs do not give latency for memory ops, but Agner has
comparable latencies for mask register loads and stores, but both
AMD and Agner say stores involve 2 uops while loads only one. Latencies
are comparable to mask <-> integer moves, so I'm not sure we should
make mask register stores cheaper than mask -> integer moves.
That said, as indicated in the other comment, mask register store cost
seems unrelated to me here.
