[Bug target/127055] Missing vectorizations of round math functions

[mkretz at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127055

--- Comment #8 from Matthias Kretz (Vir) <mkretz at gcc dot gnu.org> ---
Untested patch (currently running 'make check' in gcc):

diff --git c/gcc/config/i386/sse.md i/gcc/config/i386/sse.md
index 326d22a6d89..796c9d1d1cb 100644
--- c/gcc/config/i386/sse.md
+++ i/gcc/config/i386/sse.md
@@ -26893,13 +26893,13 @@ (define_expand "floor<mode>2"
          [(match_operand:VFH 1 "vector_operand")
           (match_dup 2)]
          UNSPEC_ROUND))]
-  "TARGET_SSE4_1 && !flag_trapping_math"
+  "TARGET_SSE4_1"
   "operands[2] = GEN_INT (ROUND_FLOOR | ROUND_NO_EXC);")

 (define_expand "lfloor<mode><sseintvecmodelower>2"
   [(match_operand:<sseintvecmode> 0 "register_operand")
    (match_operand:VHF_AVX512VL 1 "nonimmediate_operand")]
- "TARGET_AVX512FP16 && !flag_trapping_math"
+ "TARGET_AVX512FP16"
 {
   rtx tmp = gen_reg_rtx (<MODE>mode);
   emit_insn (gen_floor<mode>2 (tmp, operands[1]));
@@ -26910,7 +26910,7 @@ (define_expand "lfloor<mode><sseintvecmodelower>2"
 (define_expand "lfloor<mode><sseintvecmodelower>2"
   [(match_operand:<sseintvecmode> 0 "register_operand")
    (match_operand:VF1_VF2_AVX512DQ 1 "register_operand")]
- "TARGET_SSE4_1 && !flag_trapping_math"
+ "TARGET_SSE4_1"
 {
   rtx tmp = gen_reg_rtx (<MODE>mode);
   emit_insn (gen_floor<mode>2 (tmp, operands[1]));
@@ -26924,13 +26924,13 @@ (define_expand "ceil<mode>2"
          [(match_operand:VFH 1 "vector_operand")
           (match_dup 2)]
          UNSPEC_ROUND))]
-  "TARGET_SSE4_1 && !flag_trapping_math"
+  "TARGET_SSE4_1"
   "operands[2] = GEN_INT (ROUND_CEIL | ROUND_NO_EXC);")

 (define_expand "lceil<mode><sseintvecmodelower>2"
   [(match_operand:<sseintvecmode> 0 "register_operand")
    (match_operand:VHF_AVX512VL 1 "register_operand")]
- "TARGET_AVX512FP16 && !flag_trapping_math"
+ "TARGET_AVX512FP16"
 {
   rtx tmp = gen_reg_rtx (<MODE>mode);
   emit_insn (gen_ceil<mode>2 (tmp, operands[1]));
@@ -26941,7 +26941,7 @@ (define_expand "lceil<mode><sseintvecmodelower>2"
 (define_expand "lceil<mode><sseintvecmodelower>2"
   [(match_operand:<sseintvecmode> 0 "register_operand")
    (match_operand:VF1_VF2_AVX512DQ 1 "register_operand")]
- "TARGET_SSE4_1 && !flag_trapping_math"
+ "TARGET_SSE4_1"
 {
   rtx tmp = gen_reg_rtx (<MODE>mode);
   emit_insn (gen_ceil<mode>2 (tmp, operands[1]));
@@ -26955,7 +26955,7 @@ (define_expand "btrunc<mode>2"
          [(match_operand:VFH 1 "vector_operand")
           (match_dup 2)]
          UNSPEC_ROUND))]
-  "TARGET_SSE4_1 && !flag_trapping_math"
+  "TARGET_SSE4_1"
   "operands[2] = GEN_INT (ROUND_TRUNC | ROUND_NO_EXC);")

 (define_expand "round<mode>2"